One of actual-hardware debugging systems for checking whether or not actual hardware normally operates is a logic analyzer in which a debug circuit is inserted at mounting of a debug-target circuit, and performs debugging.
In the logic analyzer, the debug circuit monitors a signal sequence (signal transition) of the debug-target circuit designated by the user. Then, when the signal sequence matches a predetermined stop condition, the debug circuit stops operation of the circuit, and outputs the signal sequence stored in a trace memory to a display or the like.
The related techniques are disclosed in Japanese Laid-open Patent Publication Nos. 2008-250442, 2004-086910, and 2009-289106, and M. Walma, “Pipelined Cyclic Redundancy Check (CRC) Calculation”, Proc. of 16th Int'l Conf. on Computer Communications and Networks, pp. 365-370, 2007.
In the case of software debugging, a program may be stopped in response to various conditions by using break points. In contrast, in the case of hardware debugging, it is difficult to stop the hardware under conditions or at timings desired by a user due to hardware constraints such as the capacity of the trace memory and the number of signal lines usable for debugging. In such a situation, improvement in working efficiency at debugging is a challenging issue.